A Design of a Fast Parallel-Pipelined Implementation of AES: Advanced Encryption Standard

摘要

The Advanced Encryption Standard (AES) algorithm is a symmetric block cipherwhich operates on a sequence of blocks each consists of 128, 192 or 256 bits.Moreover, the cipher key for the AES algorithm is a sequence of 128, 192 or 256bits. AES algorithm has many sources of parallelism. In this paper, a design ofparallel AES on the multiprocessor platform is presented. While most of theprevious designs either use pipelined parallelization or take advantage of theMix_Column parallelization, our design is based on combining pipelining ofrounds and parallelization of Mix_Column and Add_Round_Key transformations.This model is divided into two levels: the first is pipelining differentrounds, while the second is through parallelization of both the Add_Round_Keyand the Mix_Column transformations. Previous work proposed for pipelining AESalgorithm was based on using nine stages, while, we propose the use of elevenstages in order to exploit the sources of parallelism in both initial and finalround. This enhances the system performance compared to previous designs. Usingtwo-levels of parallelization benefits from the highly independency ofAdd_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis showsthat the parallel implementation of the AES achieves a better performance. Theanalysis shows that using pipeline increases significantly the degree ofimprovement for both encryption and decryption by approximately 95%. Moreover,parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column transformationsincreases the degree of improvement by approximately 98%. This leads to theconclusion that the proposed design is scalable and is suitable for real-timeapplications.